Patterned multiple layers of thin films of metal and dielectric to form integrated circuit interconnections of transistors and/or form on-chip circuit capacitors has been used semiconductor microelectronic fabrication. Differing layers of thin film materials have different physical and thermal expansion properties. Stress occurs in multilayer film structures on a microelectronic chip, and if the film materials have different coefficients of thermal expansion, larger temperature changes will impart larger stress between the films. The amount of stress changes with temperature and according to a function of lateral feature size/area across the microelectronic chip. When the stress imparted within a patterned metal film feature becomes critically large (e.g. the yield stress is exceeded), the metal film can physically crack, buckle, and/or delaminate from other layers in the microelectronic chip. The critical stress usually damages and/or fails the intended electrical operation of the microelectronic chip. The larger the temperature range of operation and/or the larger the lateral size of the patterned metal feature, the smaller the maximum force that a patterned metal feature in the microelectronic chip endures without buckling, yielding, and/or cracking.
This concern is accentuated for integrated circuits intended to function over a broad temperature range rather than conventional integrated circuits designed for conventional (e.g. room) temperature applications (e.g. computers and/or cell phones). It is difficult to avoid stress buildup and resulting in buckling, cracking, and/or delamination damage for extreme temperature integrated circuits. Since on-chip metal-insulator-metal capacitors typically require larger lateral area metal features (i.e., the metal plates of the on-chip capacitor), the stress buildup problem is particularly acute for these devices. Stress buildup that results in detrimental damage can also occur due to metal traces (e.g. interconnects) that carry electrical signals and power throughout integrated circuits.
FIGS. 1 and 2 illustrate a prior art conventional on-chip integrated metal-insulator-metal capacitor. The implementation of an on-chip metal-insulator-metal capacitor structure uses two metal plates that are separated by a dielectric. FIGS. 1 and 2 show a prior art implementation of such a structure using prior art, wherein a large simple metal interconnect shape is employed. The metal features are patterned into simple shapes that are predominantly circular or rectangular in nature around its outer periphery wherein the interior of the shape is completely occupied by the metal. The conventional chip shows a dielectric 102 deposited onto a substrate 104. A continuous metal shape 106 is deposited onto the dielectric 102. Another dielectric 108 is deposited onto the continuous metal shape 106 such that it is covered. FIG. 2 illustrates a second metal 202 deposited onto the second dielectric 108. A third dielectric 204 is deposited onto the second metal 202 to complete a metal-insulator-metal capacitor.